Layer formation with reduced channel loss

US9000491B2 · kind B2 · utility

Assignee

• STMICROELECTRONICS, INC. · US

Inventors

• Nicolas Loubet · Guilderland, US
• Qing Liu · Guilderland, US
• Prasanna Khare · Schenectady, US

Key dates

• Filing date: Jun 19, 2014
• Grant date: Apr 7, 2015
• Expiry date: Jun 19, 2034

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/017

Abstract

Insulating layers can be formed over a semiconductor device region and etched in a manner that substantially reduces or prevents the amount of etching of the underlying channel region. A first insulating layer can be formed over a gate region and a semiconductor device region. A second insulating layer can be formed over the first insulating layer. A third insulating layer can be formed over the second insulating layer. A portion of the third insulating layer can be etched using a first etching process. A portion of the first and second insulating layers beneath the etched portion of the third insulating layer can be etched using at least a second etching process different from the first etching process.