Method for forming and integrating metal gate transistors having self-aligned contacts and related structure
US9000534B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 17, 2009 |
| Grant date | Apr 7, 2015 |
| Priority date | — |
| Expiry date | Jun 17, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0223
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
According to one exemplary embodiment, a method for forming at least one metal gate transistor with a self-aligned source/drain contact includes forming a metal gate over a substrate. The method further includes forming a source/drain region in the substrate adjacent to the metal gate. The method also includes forming a conformal etch stop layer over the metal gate and the source/drain region. The method further includes forming a source/drain contact over the source/drain region, where the conformal etch stop layer imposes a pre-determined distance between the source/drain contact and the metal gate, thereby causing the source/drain contact to be self-aligned to the metal gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.