Electronic device including shallow trench isolation (STI) regions with bottom nitride liner and upper oxide liner and related methods
US9000555B2 · kind B2 · utility
5Cited by
2References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 21, 2012 |
| Grant date | Apr 7, 2015 |
| Priority date | — |
| Expiry date | Sep 7, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76264
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An electronic device may include a substrate, a buried oxide (BOX) layer overlying the substrate, at least one semiconductor device overlying the BOX layer, and at least one STI region in the substrate and adjacent the at least one semiconductor device. The at least one STI region defines a sidewall surface with the substrate and may include a nitride layer lining a bottom portion of the sidewall surface, an oxide layer lining a top portion of the sidewall surface above the bottom portion, and an insulating material within the nitride and oxide layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.