Device with strained layer for quantum well confinement and method for manufacturing thereof
US9006705B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jun 10, 2013 |
| Grant date | Apr 14, 2015 |
| Priority date | — |
| Expiry date | Jun 10, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/832
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
The disclosed technology relates to transistors having a strained quantum well for carrier confinement, and a method for manufacturing thereof. In one aspect, a FinFET or a planar FET device comprises a semiconductor substrate, a strain-relaxed buffer layer comprising Ge formed on the semiconductor substrate, a channel layer formed on the strain-relaxed buffer layer, and a strained quantum barrier layer comprising SiGe interposed between and in contact with the strain-relaxed buffer layer and the channel layer. The compositions of the strain-relaxed buffer layer, the strained quantum barrier layer and the channel layer are chosen such that a band offset of the channel layer and a band offset of the strained quantum barrier layer have opposite signs with respect to the strain-relaxed buffer layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.