Stacked multi-chip packaging structure and manufacturing method thereof
US9006870B2 · kind B2 · utility
3Cited by
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12Claims
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Assignee
Inventors
Key dates
| Filing date | Jul 31, 2013 |
| Grant date | Apr 14, 2015 |
| Priority date | — |
| Expiry date | Aug 21, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18301
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stacked multi-chip packaging structure comprises a lead frame, a first semiconductor chip mounted on the lead frame, a second semiconductor chip flipped-chip mounted on the lead frame, a metal clip mounted on top of the first and second semiconductor chips and a third semiconductor chip stacked on the meal clip; bonding wires electrically connecting electrodes on the third semiconductor chip to the first and second semiconductor chips and the pins of the lead frame; plastic molding encapsulating the lead frame, the chips and the metal clip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.