Automatic deadlock detection and avoidance in a system interconnect by capturing internal dependencies of IP cores using high level specification
US9009648B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 18, 2013 |
| Grant date | Apr 14, 2015 |
| Priority date | — |
| Expiry date | Sep 12, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L47/12
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Systems and methods for automatically building a deadlock free inter-communication network in a multi-core system are described. The example implementations described herein involve a high level specification to capture the internal dependencies of various cores, and using it along with the user specified system traffic profile to automatically detect protocol level deadlocks in the system. When all detected deadlock are resolved or no such deadlocks are present, messages in the traffic profile between various cores of the system may be automatically mapped to the interconnect channels and detect network level deadlocks. Detected deadlocks then may be avoided by re-allocation of channel resources. An example implementation of the internal dependency specification and using it for deadlock avoidance scheme is presented on Network-on-chip interconnects for large scale multi-core system-on-chips.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.