Reducing warpage for fan-out wafer level packaging
US9012269B2 · kind B2 · utility
3Cited by
13References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 4, 2012 |
| Grant date | Apr 21, 2015 |
| Priority date | — |
| Expiry date | Jul 7, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Fan-out wafer level packaging includes an integrated circuit having a top surface, a bottom surface, a plurality of side surfaces, and a bond pad defined on the top surface. A layer of encapsulant substantially surrounds the side surfaces of the integrated circuit, the layer of encapsulant having a height substantially equal to a height of the integrated circuit. A bump is spaced apart from the integrated circuit, and a redistribution layer electrically couples the bond pad of the integrated circuit to the bump.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.