Patent · US Active

Methods of forming gate structures with multiple work functions and the resulting products

US9012319B1 · kind B1 · utility

71Cited by
3References
19Claims
0Family size

Assignee

Inventors

Key dates

Filing dateNov 1, 2013
Grant dateApr 21, 2015
Priority date—
Expiry dateNov 1, 2033

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10D84/0177
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

One illustrative method disclosed herein includes removing sacrificial gate structures for NMOS and PMOS transistors to thereby define NMOS and PMOS gate cavities, forming a high-k gate insulation layer in the NMOS and PMOS gate cavities, forming a lanthanide-based material layer on the high-k gate insulation layer in the NMOS and PMOS gate cavities, performing a heating process to drive material from the lanthanide-based material layer into the high-k gate insulation layer so as to thereby form a lanthanide-containing high-k gate insulation layer in each of the NMOS and PMOS gate cavities, and forming gate electrode structures above the lanthanide-containing high-k gate insulation layer in the NMOS and PMOS gate cavities.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.