Patent · US Active

Channel SiGe removal from PFET source/drain region for improved silicide formation in HKMG technologies without embedded SiGe

US9012956B2 · kind B2 · utility

6Cited by

6References

19Claims

0Family size

Assignee

GlobalFoundries Inc. · KY

Inventors

Stefan Flachowsky · Dresden, DE
Ralf Richter · Dresden, DE
Jan Hoentschel · Dresden, DE

Key dates

Filing date	Mar 4, 2013
Grant date	Apr 21, 2015
Priority date	—
Expiry date	Mar 20, 2033

Classification

Technology area (CPC H)Electricity
CPC primaryH10D62/822
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

When forming sophisticated P-channel transistors, a semiconductor alloy layer is formed on the surface of the semiconductor layer including the transistor active region. When a metal silicide layer is formed contiguous to this semiconductor alloy layer, an agglomeration of the metal silicide layer into isolated clusters is observed. In order to solve this problem, the present invention proposes a method and a semiconductor device wherein the portion of the semiconductor alloy layer lying on the source and drain regions of the transistor is removed before formation of the metal silicide layer is performed. In this manner, the metal silicide layer is formed so as to be contiguous to the semiconductor layer, and not to the semiconductor alloy layer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.