Load reduction dual in-line memory module (LRDIMM) and method for programming the same
US9015408B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 5, 2014 |
| Grant date | Apr 21, 2015 |
| Priority date | — |
| Expiry date | May 5, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4093
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method is disclosed for providing memory bus timing of a load reduction dual inline memory module (LRDIMM). The method includes: determining a latency value of a dynamic random access memory (DRAM) of the LRDIMM; determining a modified latency value of the DRAM that accounts for a delay caused by a load reduction buffer (LRB) that is deployed between the DRAM and a memory bus; storing the modified latency value in a serial presence detector (SPD) of the LRDIMM; and providing memory bus timing for the LRDIMM based on the modified latency value, wherein the memory bus timing is compatible with a registered dual inline memory module (RDIMM).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.