Silicon-germanium fins and silicon fins on a bulk substrate
US9029913B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 11, 2013 |
| Grant date | May 12, 2015 |
| Priority date | — |
| Expiry date | Mar 11, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/853
Abstract
A first silicon-germanium alloy layer is formed on a semiconductor substrate including silicon. A stack of a first silicon layer and a second silicon-germanium alloy layer is formed over a first region of the first silicon-germanium alloy layer, and a second silicon layer thicker than the first silicon layer is formed over a second region of the first silicon-germanium alloy layer. At least one first semiconductor fin is formed in the first region, and at least one second semiconductor fin is formed in the second region. Remaining portions of the first silicon layer are removed to provide at least one silicon-germanium alloy fin in the first region, while at least one silicon fin is provided in the second region. Fin field effect transistors can be formed on the at least one silicon-germanium alloy fin and the at least one silicon fin.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.