Read/write assist for memories
US9030863B2 · kind B2 · utility
14Cited by
5References
41Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 26, 2013 |
| Grant date | May 12, 2015 |
| Priority date | — |
| Expiry date | Sep 26, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B10/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes one or more bit cells, a word line coupled to the one or more bit cells, and a dummy word line arranged with the word line to have a capacitance therebetween. The capacitance provides a voltage boost or reduction of the word line to assist read and write operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.