Three dimensional memory array adjacent to trench sidewalls
US9035275B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 19, 2011 |
| Grant date | May 19, 2015 |
| Priority date | — |
| Expiry date | Jul 6, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8836
Abstract
A self-aligning stacked memory cell array structure and method for fabricating such structure. The memory cell array includes a stack of memory cells disposed adjacent to opposing sides of a conductive line that is formed within a trench. The memory cells are stacked such that the memory element surface of each memory cell forms a portion of the sidewall of the conductive line. The conductive line is formed within the trench such that electrical contact is made across the entire memory element surface of each memory cell. Such structure and method for making such structure is a self-aligning process that does not require the use of any additional masks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.