Flash memory techniques for recovering from write interrupt resulting from voltage fault
US9037902B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 15, 2013 |
| Grant date | May 19, 2015 |
| Priority date | — |
| Expiry date | Nov 28, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1666
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques, related to a flash memory device having a non-volatile memory array (NVM), for recovering from a write interrupt resulting from host-supplied memory voltage fault are disclosed. A memory controller is configured to control a response to an occurrence of the write-interrupt, the response including writing to the NVM, after the memory voltage is verified as being within an acceptable range, one or more of a safe copy of a portion of a first sector of upper-page data and a safe copy of a portion of a second sector of lower-page data, and terminating the write interrupt. Terminating the write-interrupt may include receiving new data from the host while avoiding sending an error message to the host.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.