Partial sacrificial dummy gate with CMOS device with high-k metal gate
US9041076B2 · kind B2 · utility
3Cited by
11References
16Claims
0Family size
Assignee
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Key dates
| Filing date | Feb 3, 2013 |
| Grant date | May 26, 2015 |
| Priority date | — |
| Expiry date | Jul 8, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/021
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A gate structure in a semiconductor device includes: a gate stack formed on a substrate with three sections: a bottom portion, a top portion, and a sacrificial cap layer over the top portion; gate spacers; source and drain regions; a nitride encapsulation over top and sidewalls of the gate stack after removal of the sacrificial cap layer; an organic planarizing layer over the nitride encapsulation, planarizing the encapsulation; and silicidation performed over the source and drain regions and the bottom portion after removal of the nitride encapsulation, the organic planarizing layer, and the top portion of the gate stack.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.