Chip edge sealing
US9054150B2 · kind B2 · utility
0Cited by
4References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 20, 2013 |
| Grant date | Jun 9, 2015 |
| Priority date | — |
| Expiry date | Sep 20, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/117
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention relates to a semiconductor component comprising a semiconductor body, an insulation on the semiconductor body and a cell array arranged at least partly within the semiconductor body. The cell array has at least one p-n junction and at least one contact connection. The insulation is bounded in lateral direction of the semiconductor body by a circumferential diffusion barrier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.