Resistance-based random access memory
US9058872B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 31, 2013 |
| Grant date | Jun 16, 2015 |
| Priority date | — |
| Expiry date | Feb 25, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A resistance-based random access memory circuit includes a first data line, a second data line, a plurality of memory cells, a first driving unit, and a second driving unit. The memory cells are arranged one following another in parallel with the first and second data lines. Each of the memory cells are coupled between the first data line and the second data line. The first driving unit is coupled with first ends of the first and second data lines. The first driving unit is configured to electrically couple one of the first data line and the second data line to a first voltage node. The second driving unit is coupled with second ends of the first and second data lines. The second driving unit is configured to electrically couple the other one of the first data line and the second data line to a second voltage node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.