Inline measurement of through-silicon via depth

US9059051B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Hanyi Ding · Colchester, US
• J. Edwin Hostetter · Pleasant Valley, US
• Ping-Chuan Wang · Hopewell Junction, US
• Kimball M. Watson · South Burlington, US

Key dates

• Filing date: May 8, 2013
• Grant date: Jun 16, 2015
• Expiry date: Jul 12, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L22/34
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A through-silicon via (TSV) capacitive test structure and method of determining TSV depth based on capacitance is disclosed. The TSV capacitive test structure is formed from a plurality of TSV bars that are evenly spaced. A first group of bars are electrically connected to form a first capacitor node, and a second group of bars is electrically connected to form a second capacitor node. The capacitance is measured, and a TSV depth is computed, prior to backside thinning. The computed TSV depth may then be fed to downstream grinding and/or polishing tools to control the backside thinning process such that the semiconductor wafer is thinned such that the backside is flush with the TSV.