Integrated circuit packaging system with substrate and method of manufacture thereof
US9059157B2 · kind B2 · utility
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11References
20Claims
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Key dates
| Filing date | Mar 15, 2013 |
| Grant date | Jun 16, 2015 |
| Priority date | — |
| Expiry date | Mar 15, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit packaging system and method of manufacture thereof includes: a substrate having a top insulation layer and a top conductive layer; an inter-react layer on the substrate; an integrated circuit die on the substrate; a package body on the inter-react layer and the integrated circuit die; and a top solder bump on the top conductive layer, the top solder bump in a 3D via formed through the package body, the inter-react layer, and the top insulation layer for exposing the top conductive layer in the 3D via.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.