Memory devices with local and global devices at substantially the same level above stacked tiers of memory cells and methods
US9070442B2 · kind B2 · utility
17Cited by
5References
42Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 29, 2013 |
| Grant date | Jun 30, 2015 |
| Priority date | — |
| Expiry date | Dec 24, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49069
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an embodiment, a memory device includes a stack of tiers of memory cells, a tier of local devices at a level above the stack of tiers of memory cells, and a tier of global devices at substantially a same level as the tier of local devices. A local device may provide selective access to a data line. A global device may provide selective access to a global access line. A tier of memory cells may be selectively coupled to a global access line by the global device of the tier of global devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.