Stacked semiconductor die with continuous conductive vias
US9076664B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 7, 2011 |
| Grant date | Jul 7, 2015 |
| Priority date | — |
| Expiry date | Oct 11, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06589
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stacked semiconductor device includes a first, a second, a third, and a fourth semiconductor device. A first major surface of each of the first and second semiconductor devices which includes the active circuitry directly face each other, and a first major surface of each of the third and fourth semiconductor devices which includes the active circuitry directly face each other. A second major surface of the second semiconductor device directly faces a second major surface of the third semiconductor device. The stacked semiconductor device includes a plurality of continuous conductive vias, wherein each continuous conductive via extends from the second major surface of the first device, through the first device, second device, third device, and fourth device to the second major surface of the fourth device. Each of the semiconductor devices may include a beveled edge at the first major surface on at least one edge of the device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.