Enhanced dislocation stress transistor
US9076814B2 · kind B2 · utility
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16Claims
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Key dates
| Filing date | Jun 6, 2014 |
| Grant date | Jul 7, 2015 |
| Priority date | — |
| Expiry date | Jun 6, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/259
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A device is provided. The device includes a transistor formed on a semiconductor substrate, the transistor having a conduction channel. The device includes at least one edge dislocation formed adjacent to the conduction channel on the semiconductor substrate. The device also includes at least one free surface introduced above the conduction channel and the at least one edge dislocation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.