Non-volatile memory with vertical selection transistors
US9076878B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 1, 2013 |
| Grant date | Jul 7, 2015 |
| Priority date | — |
| Expiry date | Dec 25, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to a method for manufacturing a non-volatile memory on a semiconductive substrate, comprising the steps of implanting in the depth of the substrate a first doped region forming a source region of selection transistors, forming in the substrate a buried gate comprising deep parts extending between an upper face of the substrate and the first doped region, implanting between two adjacent deep parts of the buried gate, a second doped region forming a common drain region of common selection transistors of a pair of memory cells, the selection transistors of the pair of memory cells thus having channel regions extending between the first doped region and the second doped region, along faces opposite the two buried gate adjacent deep parts, and implanting along opposite upper edges of the buried gate, third doped regions forming source regions of charge accumulation transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.