Semiconductor device and method of forming a robust fan-out package including vertical interconnects and mechanical support layer
US9082780B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 23, 2012 |
| Grant date | Jul 14, 2015 |
| Priority date | — |
| Expiry date | Jul 14, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device has a semiconductor die. An encapsulant is deposited around the semiconductor die. An interconnect structure having a conductive bump is formed over the encapsulant and semiconductor die. A mechanical support layer is formed over the interconnect structure and around the conductive bump. The mechanical support layer is formed over a corner of the semiconductor die and over a corner of the interconnect structure. An opening is formed through the encapsulant that extends to the interconnect structure. A conductive material is deposited within the opening to form a conductive through encapsulant via (TEV) that is electrically connected to the interconnect structure. A semiconductor device is mounted to the TEV and over the semiconductor die to form a package-on-package (PoP) device. A warpage balance layer is formed over the encapsulant opposite the interconnect structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.