Electroless fill of trench in semiconductor structure
US9087881B2 · kind B2 · utility
4Cited by
2References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 5, 2013 |
| Grant date | Jul 21, 2015 |
| Priority date | — |
| Expiry date | May 18, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A trench in an inter-layer dielectric formed on a semiconductor substrate is defined by a bottom and sidewalls. A copper barrier lines the trench with a copper-growth-promoting liner over the barrier. The trench has bulk copper filling it, and includes voids in the copper. The copper with voids is removed, including from the sidewalls, leaving a void-free copper portion at the bottom. Immersion in an electroless copper bath promotes upward growth of copper on top of the void-free copper portion without inward sidewall copper growth, resulting in a void-free copper fill of the trench.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.