Methods of forming substantially self-aligned isolation regions on FinFET semiconductor devices and the resulting devices

US9093302B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Ruilong Xie · Niskayuna, US
• Vimal Kamineni · Mechanicville, US
• Abner Bello · Clifton Park, US
• Nicholas V. LiCausi · Watervliet, US
• Wenhui Wang · Clifton Park, US
• Michael Wedlake · Albany, US
• Jason R. Cantone · Mechanicville, US

Key dates

• Filing date: Nov 13, 2013
• Grant date: Jul 28, 2015
• Expiry date: Jan 14, 2034

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/6219
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

One method disclosed includes performing a selective etching process through a gate cavity to selectively remove a portion of a first semiconductor material relative to a second layer of a second semiconductor material and a substrate so as to thereby define a space between the second semiconducting material and the substrate, filling substantially all of the space with an insulating material so as to thereby define a substantially self-aligned channel isolation region positioned under at least what will become the channel region of the FinFET device.