Methods of forming gate structures for semiconductor devices using a replacement gate technique and the resulting devices
US9093467B1 · kind B1 · utility
55Cited by
3References
8Claims
0Family size
Assignee
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Key dates
| Filing date | Feb 4, 2014 |
| Grant date | Jul 28, 2015 |
| Priority date | — |
| Expiry date | Feb 4, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0275
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
One method and device disclosed includes, among other things, forming a recessed sacrificial gate electrode having a recessed upper surface, performing at least one second etching process to define recessed sidewall spacers positioned adjacent the recessed sacrificial gate electrode, forming a plurality of sidewall spacers within a gate opening above the recessed sidewall spacers, wherein one of the spacers comprises a low-k insulating material that is positioned laterally between two other spacers and a gate cap layer, removing the recessed sacrificial gate electrode and forming a replacement gate structure in its place.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.