Vertical power MOSFET with planar channel and vertical field plate
US9093522B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 22, 2014 |
| Grant date | Jul 28, 2015 |
| Priority date | — |
| Expiry date | Jul 22, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/518
Abstract
A power MOSFET cell includes an N+ silicon substrate having a drain electrode. A low dopant concentration N-type drift layer is grown over the substrate. Alternating N and P-type columns are formed over the drift layer with a higher dopant concentration. An N-type layer, having a higher dopant concentration than the drift region, is then formed and etched to have sidewalls. A P-well is formed in the N-type layer, and an N+ source region is formed in the P-well. A gate is formed over the P-well's lateral channel and next to the sidewalls as a vertical field plate. A source electrode contacts the P-well and source region. A positive gate voltage inverts the lateral channel and increases the conduction along the sidewalls. Current between the source and drain flows laterally and then vertically through the various N layers. On resistance is reduced and the breakdown voltage is increased.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.