Gate height uniformity in semiconductor devices

US9093560B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Tsung-Liang Chen · Zhubeikou, TW
• Hung-Wei Liu · Jinshanmian, TW
• Rohit Pal · Fishkill, US
• Hsin-Neng Tai · Clifton Park, US
• Huey-Ming Wang · Fremont, US
• Tae Hoon Lee · Clifton Park, US
• Songkram Srivathanakul · Cohoes, US
• Danni Chen · Clifton Park, US

Key dates

• Filing date: Sep 20, 2013
• Grant date: Jul 28, 2015
• Expiry date: Oct 6, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/8316

Abstract

Methods of facilitating gate height uniformity by controlling recessing of dielectric material and semiconductor devices formed from the methods are provided. The methods include, for instance, forming a transistor of the semiconductor device with an n-type transistor and a p-type transistor, the n-type transistor and the p-type transistor including plurality of sacrificial gate structures and protective masks at upper surfaces of the plurality of sacrificial gate structures; providing a dielectric material over and between the plurality of sacrificial gate structures; partially densifying the dielectric material to form a partially densified dielectric material; further densifying the partially densified dielectric material to create a modified dielectric material; and creating substantially planar surface on the modified dielectric material, to control dielectric material recess and gate height.