Test method and test arrangement

US9099419B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Markus Zundel · Egmating, DE
• Franz Hirler · Isen, DE
• Peter Nelle · Munich, DE

Key dates

• Filing date: Oct 9, 2012
• Grant date: Aug 4, 2015
• Expiry date: Jun 4, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/0002
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

A test method in accordance with one or more embodiments may include: providing a semiconductor device to be tested, the semiconductor device including at least one device cell, the at least one device cell having at least one trench, at least one first terminal electrode region and at least one second terminal electrode region, at least one gate electrode, and at least one additional electrode disposed at least partially in the at least one trench, wherein an electrical potential of the at least one additional electrode may be controlled separately from electrical potentials of the at least one first terminal electrode region, the at least one second terminal electrode region and the at least one gate electrode; and applying at least one electrical test potential to at least the at least one additional electrode to detect defects in the at least one device cell.