Method of forming an active area with floating gate negative offset profile in FG NAND memory

US9099496B2 · kind B2 · utility

Assignee

• Sandisk Technologies, Inc. · US

Inventors

• Ming Tian · Nanhu, CN
• Jayavel Pachamuthu · Milpitas, US
• Atsushi Suyama · Osaka, JP
• James Kai · Santa Clara, US
• Raghuveer S. Makala · Campbell, US
• Yao-Sheng Lee · Tampa, US
• Johann Alsmeier · San Jose, US
• Henry Chien · San Jose, US
• Masanori Terahara · Yokkaichi, JP
• Hirofumi Watatani · Kawasaki, JP

Key dates

• Filing date: Aug 29, 2014
• Grant date: Aug 4, 2015
• Expiry date: Aug 29, 2034

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/693

Abstract

A stack can be patterned by a first etch process to form an opening defining sidewall surfaces of a patterned material stack. A masking layer can be non-conformally deposited on sidewalls of an upper portion of the patterned material stack, while not being deposited on sidewalls of a lower portion of the patterned material stack. The sidewalls of a lower portion of the opening can be laterally recessed employing a second etch process, which can include an isotropic etch component. The sidewalls of the upper portion of the opening can protrude inward toward the opening to form an overhang over the sidewalls of the lower portion of the opening. The overhang can be employed to form useful structures such as an negative offset profile in a floating gate device or vertically aligned control gate electrodes for vertical memory devices.