Processes for NAND flash memory fabrication
US9099532B2 · kind B2 · utility
4Cited by
11References
8Claims
0Family size
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Key dates
| Filing date | Feb 22, 2013 |
| Grant date | Aug 4, 2015 |
| Priority date | — |
| Expiry date | Mar 29, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/41
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Narrow word lines are formed in a NAND flash memory array using a double patterning process in which sidewall spacers define word lines. Sidewall spacers also define edges of select gates so that spacing between a select gate and the closest word line is equal to spacing between adjacent word lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.