Load balancing for optimal tessellation performance
US9105125B2 · kind B2 · utility
7Cited by
3References
23Claims
0Family size
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Key dates
| Filing date | Dec 5, 2012 |
| Grant date | Aug 11, 2015 |
| Priority date | — |
| Expiry date | Apr 1, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2360/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system, method and a computer-readable medium for load balancing patch processing pre-tessellation are provided. The patches for drawing objects on a display screen are distributed to shader engines for parallel processing. Each shader engine generates tessellation factors for a patch, wherein a value of generated tessellation factors for the patch is unknown prior to distribution. The patches are redistributed to the shader engines pre-tessellation to load balance the shader engines for processing the patches based on the value of tessellation factors in each patch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.