Patent · US Active

Integrated circuit package and packaging methods

US9105562B2 · kind B2 · utility

0Cited by

4References

11Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Georg Meyer-Berg · Birkenfeld, DE
Frank Daeche · Unterhaching, DE

Key dates

Filing date	Dec 15, 2011
Grant date	Aug 11, 2015
Priority date	—
Expiry date	Nov 20, 2033

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/15311
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

An integrated circuit packaging method includes fabricating a package module from successive build-up layers which define circuit interconnections, forming a cavity on a top-side of the package module, attaching a metalized back-side of a chip onto a metallic layer, the chip having a front-side with at least one forward contact, disposing the chip in the cavity such that at least one forward contact is electrically connected to at least one of the circuit interconnections of the package module, and coupling the metallic layer that is attached to the chip onto the top-side of the package module.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.