MRAM smart bit write algorithm with error correction parity bits
US9110829B2 · kind B2 · utility
6Cited by
4References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 14, 2013 |
| Grant date | Aug 18, 2015 |
| Priority date | — |
| Expiry date | Nov 6, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2013/0076
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Some aspects of the present disclosure relate a method. The method attempts to write an expected multi-bit word to a memory location in memory. After writing of the multi-bit word has been attempted, an actual multi-bit word is read from the memory location. The actual multi-bit word is then compared with the expected multi-bit word to identify a number of erroneous bits and a number of correct bits stored in the memory location. The number of erroneous bits is re-written to the memory location without attempting to re-write the correct bits to the memory location.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.