Memory timing circuit
US9111589B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 4, 2013 |
| Grant date | Aug 18, 2015 |
| Priority date | — |
| Expiry date | Nov 26, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/227
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed are various apparatuses and methods for a memory with a multiple word line design. A memory timing circuit may include a dummy word line including a first portion and a second portion and further including capacitative loading that is lumped in the second portion of the dummy word line, a first transistor connected to the first portion of the dummy word line and configured to charge the dummy word line, and a second transistor connected to the second portion of the dummy word line and configured to discharge the dummy word line. A method may include charging a dummy word line using a first transistor, and discharging the dummy word line using a second transistor, wherein the dummy word line includes a first portion and a second portion and further includes capacitative loading that is lumped in the second portion of the dummy word line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.