Method for reducing damage to low-k gate spacer during etching
US9111746B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 18, 2012 |
| Grant date | Aug 18, 2015 |
| Priority date | — |
| Expiry date | Aug 18, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for performing a spacer etch process is described. The method includes providing a gate structure on a substrate having a low-k spacer material conformally applied over the gate structure, and performing a spacer etch process sequence to partially remove the spacer material from the gate structure and the substrate, while retaining a sidewall spacer positioned along a sidewall of the gate structure. The spacer etch process sequence may include depositing a spacer protection layer on an exposed surface of said spacer material, and performing one or more etching processes to selectively and anisotropically remove the spacer protection layer and the spacer material to leave behind the sidewall spacer on the sidewall of the gate structure, wherein, while being partly or fully consumed by the one or more etching processes, the spacer protection layer exhibits a reduced variation in composition and/or dielectric constant.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.