Electronic array and chip package

US9111772B1 · kind B1 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Volker Strutz · Tegernheim, DE
• Horst Theuss · Wenzenbach, DE
• Chee Voon Tan · Seremban, MY
• Hui Teng Wang · Muar, MY

Key dates

• Filing date: Jan 29, 2014
• Grant date: Aug 18, 2015
• Expiry date: Feb 14, 2034

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/00014
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

An electronic array may include a first electronic component which has a first operation voltage, a second electronic component which has a second operation voltage, wherein the second operation voltage is different from the first operation voltage and wherein the first electronic component and the second electronic component are arranged over each other, an isolation layer between the first electronic component and the second electronic component, wherein the isolation layer electrically isolates the first electronic component from the second electronic component, at least one connection layer formed at least partially between the isolation layer and the first electronic component or between the isolation layer and the second electronic component, wherein the connection layer includes a first portion and a second portion, wherein the first portion and the second portion each extend from the corresponding electronic component to the isolation layer, wherein the first portion includes an electrically isolating material which fixes the isolation layer to the corresponding electronic component and wherein the second portion includes an electrically conductive material which electrical…