CMOS implementation of germanium and III-V nanowires and nanoribbons in gate-all-around architecture

US9123567B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Marko Radosavljevic · Portland, US
• Ravi Pillarisetty · Portland, US
• Gilbert Dewey · Beaverton, US
• Niloy Mukherjee · Beaverton, US
• Jack T. Kavalieros · Portland, US
• Willy Rachmady · Beaverton, US
• Van H. Le · Portland, US
• Benjamin Chu-Kung · Portland, US
• Matthew V. Metz · Portland, US
• Robert S. Chau · Beaverton, US

Key dates

• Filing date: Dec 19, 2011
• Grant date: Sep 1, 2015
• Expiry date: Jan 11, 2032

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0167
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Architectures and techniques for co-integration of heterogeneous materials, such as group III-V semiconductor materials and group IV semiconductors (e.g., Ge) on a same substrate (e.g. silicon). In embodiments, multi-layer heterogeneous semiconductor material stacks having alternating nanowire and sacrificial layers are employed to release nanowires and permit formation of a coaxial gate structure that completely surrounds a channel region of the nanowire transistor. In embodiments, individual PMOS and NMOS channel semiconductor materials are co-integrated with a starting substrate having a blanket layers of alternating Ge/III-V layers. In embodiments, vertical integration of a plurality of stacked nanowires within an individual PMOS and individual NMOS device enable significant drive current for a given layout area.