Contact techniques and configurations for reducing parasitic resistance in nanowire transistors

US9123790B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Ravi Pillarisetty · Portland, US
• Benjamin Chu-Kung · Portland, US
• Willy Rachmady · Beaverton, US
• Van H. Le · Portland, US
• Gilbert Dewey · Beaverton, US
• Niloy Mukherjee · Beaverton, US
• Matthew V. Metz · Portland, US
• Han Wui Then · Portland, US
• Marko Radosavljevic · Portland, US

Key dates

• Filing date: Dec 28, 2011
• Grant date: Sep 1, 2015
• Expiry date: Apr 1, 2032

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S977/89
• WIPO field: Micro-structural and nano-technology
• WIPO sector: Chemistry

Abstract

Embodiments of the present disclosure provide contact techniques and configurations for reducing parasitic resistance in nanowire transistors. In one embodiment, an apparatus includes a semiconductor substrate, an isolation layer formed on the semiconductor substrate, a channel layer including nanowire material formed on the isolation layer to provide a channel for a transistor, and a contact coupled with the channel layer, the contact being configured to surround, in at least one planar dimension, nanowire material of the channel layer and to provide a source terminal or drain terminal for the transistor.