Deep gate-all-around semiconductor device having germanium or group III-V active layer

US9136343B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Ravi Pillarisetty · Portland, US
• Willy Rachmady · Beaverton, US
• Van H. Le · Portland, US
• Seung Hoon Sung · Beaverton, US
• Jessica S. Kachian · Portland, US
• Jack T. Kavalieros · Portland, US
• Han Wui Then · Portland, US
• Gilbert Dewey · Beaverton, US
• Marko Radosavljevic · Portland, US
• Benjamin Chu-Kung · Portland, US
• Niloy Mukherjee · Beaverton, US

Key dates

• Filing date: Jan 24, 2013
• Grant date: Sep 15, 2015
• Expiry date: Mar 8, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/824

Abstract

Deep gate-all-around semiconductor devices having germanium or group III-V active layers are described. For example, a non-planar semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a hetero-junction between an upper layer and a lower layer of differing composition. An active layer is disposed above the hetero-structure and has a composition different from the upper and lower layers of the hetero-structure. A gate electrode stack is disposed on and completely surrounds a channel region of the active layer, and is disposed in a trench in the upper layer and at least partially in the lower layer of the hetero-structure. Source and drain regions are disposed in the active layer and in the upper layer, but not in the lower layer, on either side of the gate electrode stack.