Transistor with coupled gate and ground plane
US9136366B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jan 16, 2014 |
| Grant date | Sep 15, 2015 |
| Priority date | — |
| Expiry date | Jan 16, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6757
Abstract
An integrated circuit includes a silicon substrate, a ground plane above the substrate, a buried insulator layer above the ground plane, a silicon layer above the buried insulator layer and separated from the ground plane by the buried insulator layer, and an FDSOI transistor. The transistor has a channel adapted for being formed in the silicon layer, a source and drain in and/or on the silicon layer, and a gate covering an upper face of the channel and having a lateral portion covering a lateral face of the channel and above the ground plane. A distance between the lateral portion and the ground plane is not more than three nanometers and at least five times less than a thickness of the buried insulator layer between the ground plane and the silicon layer. The ground plane is separated from the gate by the buried insulator layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.