Method for generating layout pattern
US9141744B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 15, 2013 |
| Grant date | Sep 22, 2015 |
| Priority date | — |
| Expiry date | Aug 15, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F1/36
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for generating a layout pattern is provided. First, a layout pattern is provided to a computer system and is classified into two sub-patterns and a blank pattern. Each of the sub-patterns has pitches in simple integer ratios and the blank pattern is between the two sub-patterns. Then, a plurality of first stripe patterns and at least two second stripe patterns are generated. The edges of the first stripe patterns are aligned with the edges of the sub-patterns and the first stripe patterns have equal spacings and widths. The spacings or widths of the second stripe patterns are different from that of the first stripe patterns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.