Memory circuitry using write assist voltage boost
US9142266B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 19, 2013 |
| Grant date | Sep 22, 2015 |
| Priority date | — |
| Expiry date | Nov 19, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Within a memory 2 comprising an array 4 of bit cells 6 write driver circuitry 14 uses a boosted write signal which is boosted to a lower than normal level during a write operation. Column select transistors 16 are driven by column select circuitry 12. The column select signal is boosted to a lower than normal level when a column is unselected and to higher than a normal level when a column is selected. Voltage boost circuitry, such as charge pumps 20, 22 are employed within the column select circuitry 12 to achieve these boosted levels for the columns select signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.