Bad block reconfiguration in nonvolatile memory
US9142324B2 · kind B2 · utility
4Cited by
19References
23Claims
0Family size
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Key dates
| Filing date | Sep 3, 2013 |
| Grant date | Sep 22, 2015 |
| Priority date | — |
| Expiry date | Feb 21, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/44
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
When a bad block is found in a nonvolatile memory array, the block is marked as a bad block so that it is not subsequently used. The block is also reconfigured as a bad block by increasing resistance of vertical NAND strings in the block by increasing threshold voltage of at least some transistors along vertical NAND strings, for example, select transistors or memory cell transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.