3D interconnect structure comprising through-silicon vias combined with fine pitch backside metal redistribution lines fabricated using a dual damascene type approach

US9142510B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Kevin J. Lee · Beaverton, US
• Mark Bohr · Beaverton, US
• Andrew W. Yeoh · Portland, US
• Christopher M. Pelto · Beaverton, US
• Hiten Kothari · Beaverton, US
• Seshu V. Sattiraju · Portland, US
• Hang-Shing Ma · Portland, US

Key dates

• Filing date: Oct 28, 2011
• Grant date: Sep 22, 2015
• Expiry date: Feb 15, 2032

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/381
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A 3D interconnect structure and method of manufacture are described in which a through-silicon vias (TSVs) and metal redistribution layers (RDLs) are formed using a dual damascene type process flow. A silicon nitride or silicon carbide passivation layer may be provided between the thinned device wafer back side and the RDLs to provide a hermetic barrier and etch stop layer during the process flow.