Integrated circuits and methods for fabricating integrated circuits with silicide contacts on non-planar structures
US9142633B2 · kind B2 · utility
5Cited by
1References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 13, 2012 |
| Grant date | Sep 22, 2015 |
| Priority date | — |
| Expiry date | Feb 26, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6219
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate and forming fins over the semiconductor substrate. Each fin is formed with sidewalls. The method further includes conformally depositing a metal film stack on the sidewalls of each fin. In the method, the metal film stack is annealed to form a metal silicide film over the sidewalls of each fin.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.