Etch process for reducing directed self assembly pattern defectivity using direct current positioning
US9153457B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 4, 2013 |
| Grant date | Oct 6, 2015 |
| Priority date | — |
| Expiry date | Oct 31, 2033 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB81C2201/0149
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for preparing a patterned directed self-assembly layer for reducing directed self-assembly pattern defectivity using direct current superpositioning is provided. A substrate having a block copolymer layer overlying a first intermediate layer, said block copolymer layer comprising a first phase-separated polymer defining a first pattern and a second phase-separated polymer defining a second pattern in said block copolymer layer is provided. A first plasma etching process using plasma formed of a first process composition to remove said second phase-separated polymer while leaving behind said first pattern of said first phase-separated polymer is performed. A second plasma etching process to transfer said first pattern into said first intermediate layer using plasma formed of a second process composition is performed. In an embodiment, said first phase-separated polymer is exposed to an electron beam preceding, during, or following said first plasma etching process, or preceding or during said second plasma etching process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.