CVD based metal/semiconductor OHMIC contact for high volume manufacturing applications
US9153486B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 12, 2013 |
| Grant date | Oct 6, 2015 |
| Priority date | — |
| Expiry date | Apr 12, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for manufacturing an interconnect structure to provide ohmic contact in a semiconductor device is provided. The method includes providing a semiconductor device, such as a transistor, comprising a substrate, a gate dielectric, a gate electrode, and source and drain regions in the substrate. An ultra-thin interfacial dielectric is deposited by chemical vapor deposition (CVD) over the source and drain regions, where the interfacial dielectric can have a thickness between about 3 Å and about 20 Å. The ultra-thin interfacial dielectric is configured to unpin the metal Fermi level from the source and drain regions. Other steps such as the deposition of a metal by CVD and the cleaning of the substrate surface can be performed in an integrated process tool without a vacuum break. The method further includes forming one or more vias through a pre-metal dielectric over the source and drain regions of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.