Methods of making word lines and select lines in NAND flash memory
US9153595B2 · kind B2 · utility
0Cited by
6References
13Claims
0Family size
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Key dates
| Filing date | Sep 14, 2012 |
| Grant date | Oct 6, 2015 |
| Priority date | — |
| Expiry date | Feb 14, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
Abstract
A NAND flash memory chip includes word lines formed by etching through concentric conductive loops and, in the same etch step, etching through a conductive strip to form select lines. A conductive loop forms two word lines which are in different erase blocks and are separately controlled by peripheral circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.